Digital and Mixed Signal circuitry typically uses clock signals including a system clock and clocks derived from the system clock. PLL, delay lock loop (DLL) or FLL circuits are employed to compare the system clock with a reference clock source, and to adjust the frequency of the system clock to ideally match or “lock” the system clock frequency with that of the reference. Cell phones and other portable electronic devices are often designed to operate at different clock frequencies. For example, a cell phone may change from a 2.5G network to a 3G network, requiring switch over from one reference clock/PLL circuit to another. Other examples include redundant clock systems in which a primary reference clock source may be disabled requiring switch over to a different reference source, or MP3 track sample rates may change in an audio device. In such cases, conventional clock circuits provide a dedicated PLL or FLL for each reference clock source, and multiple sets of reference clock sources and corresponding PLL or FLL circuits are needed. In addition, a clock handover circuit is required, which can lead to a few clock cycles of glitch during the handover. Moreover, changing from the output of one PLL to another PLL associated with the backup or secondary reference clock source requires the system to undergo transitory circuit behavior or glitch while output of the new clock reference/PLL circuit settles. Thus, a need remains for improved low cost clock circuits operable according to one of a plurality of reference clock sources while mitigating glitch and settling time associated with conventional clock handover circuits.